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Studies in Computational Intelligence Ser.: Robotic Exploration and Landmark Determination : Hardware-Efficient Algorithms and FPGA Implementations by Panakala Rajesh Kumar and Krishnamurthy Sridharan (2008, Mixed Lot)
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- Buy It NowRobotic Exploration and Landmark Determination: Hardware-Efficient Algorithms
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About this product
Product Identifiers
PublisherSpringer Berlin / Heidelberg
ISBN-103540753931
ISBN-139783540753933
eBay Product ID (ePID)63887156
Product Key Features
Number of PagesXiii, 139 Pages
LanguageEnglish
Publication NameRobotic Exploration and Landmark Determination : Hardware-Efficient Algorithms and FPGA Implementations
SubjectEngineering (General), Intelligence (Ai) & Semantics, Life Sciences / Anatomy & Physiology (See Also Life Sciences / Human Anatomy & Physiology), Electrical, Applied, Robotics
Publication Year2008
TypeTextbook
Subject AreaMathematics, Computers, Technology & Engineering, Science
AuthorPanakala Rajesh Kumar, Krishnamurthy Sridharan
SeriesStudies in Computational Intelligence Ser.
FormatMixed Lot
Dimensions
Item Weight14.1 Oz
Item Length9.3 in
Item Width6.1 in
Additional Product Features
Intended AudienceScholarly & Professional
Dewey Edition22
Series Volume Number81
Number of Volumes1 vol.
IllustratedYes
Dewey Decimal629.892
Table Of ContentLiterature Survey.- Design and Development of an FPGA-based Robot.- Hardware-Efficient Robotic Exploration.- Hardware-Efficient Landmark Determination.- The Road Ahead.
SynopsisMuch of the research effort in mobile robots in the recent past has been on sensing and design of time-efficient algorithms for tasks such as localization, mapping and navigation. Mobile robots typically employ an embedded computer for high level computations. As applications of robots expand, there is a need to investigate architecturally efficient choices for this embedded computing platform. In particular, it is valuable to process data to obtain time, space and energy-efficient solutions for various robotic tasks. This book presents hardware-efficient algorithms and FPGA implementations for two robotic tasks, namely exploration and landmark determination. The work identifies scenarios for mobile robotics where parallel processing and selective shutdown offered by FPGAs are invaluable. The book proceeds to systematically develop memory-driven VLSI architectures for both the tasks. The architectures are ported to a low-cost FPGA with a fairly small number of system gates. A robot fabricated with this FPGA on-board serves to validate the efficacy of the approach. Numerous experiments with the robot are reported., Literature Survey.- Design and Development of an FPGA-based Robot.- Hardware-Efficient Robotic Exploration.- Hardware-Efficient Landmark Determination.- The Road Ahead., This book presents hardware-efficient algorithms and FPGA implementations for two robotic tasks, namely exploration and landmark determination. The work identifies scenarios for mobile robotics where parallel processing and selective shutdown offered by FPGAs are invaluable. The book proceeds to systematically develop memory-driven VLSI architectures for both the tasks. The architectures are ported to a low-cost FPGA with a fairly small number of system gates.
LC Classification NumberTJ212-225
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