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PA-RISC 2. 0 Architecture by Packard C Hewlett, Hewlett-Packard Professional Books Staff and Gerry Kane (1995, Trade Paperback)

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About this product

Product Identifiers

PublisherPrentice Hall PTR

ISBN-100131827340

ISBN-139780131827349

eBay Product ID (ePID)46119

Product Key Features

Number of Pages496 Pages

LanguageEnglish

Publication NamePa-Risc 2. 0 Architecture

SubjectSystems Architecture / General, Microprocessors, Hardware / Personal Computers / General

Publication Year1995

TypeTextbook

AuthorPackard C Hewlett, Hewlett-Packard Professional Books Staff, Gerry Kane

Subject AreaComputers

FormatTrade Paperback

Dimensions

Item Height0.7 in

Item Weight27.2 Oz

Item Length7 in

Item Width9.3 in

Additional Product Features

Intended AudienceScholarly & Professional

LCCN95-049176

Dewey Edition20

IllustratedYes

Dewey Decimal004.1

Table Of Content1. Overview. Traditional RISC Characteristics of PA-RISC. PA-RISC-The Genius is in the Details. A Critical Calculus: Instruction Pathlength. Multimedia Support: The Precision Process Illustrated. Integrated CPU. Extensibility and Longevity. System Organization. 2. Processing Resources. Non-Privileged Software-Accessible Registers. Privileged Software-Accessible Registers. Unused Registers and Bits. Data Types. Byte Ordering (Big Endian/Little Endian). 3. Addressing and Access Control. Physical and Absolute Addressing. Virtual Addressing. Pointers and Address Specification. Address Resolution and the TLB. Access Control. 4. Page Table Structure. Caches. Control Flow. Branching. Nullification. Instruction Execution. Instruction Pipelining. 5. Interruptions. Interrupt Classes. Interruption Handling. Instruction Recoverability. Masking and Nesting of Interruptions. Interruption Priorities. Return from Interruption. Interruption Descriptions. 6. Instruction Set Overview. Computation Instructions. Multimedia Instructions. Memory Reference Instructions. Long Immediate Instructions. Branch Instructions. System Control Instructions. Assist Instructions. Conditions and Control Flow. Additional Notes on the Instruction Set. 7. Instruction Descriptions. 8. Floating-point Coprocessor. The IEEE Standard. The Instruction Set. Coprocessor Registers. Data Registers. Data Formats. Floating-Point Status Register. Floating-Point Instruction Set. 9. Floating-Point Instruction Set. 10. Floating-Point Exceptions. Exception Registers. Interruptions and Exceptions. Saving and Restoring State. 11. Performance Monitor Coprocessor. Performance Monitor Instructions. Performance Monitor Interruptions. Monitor Units. Glossary. Appendix B. Instruction Formats. Appendix C. Operation Codes. Appendix D. Conditions. Appendix E. Instruction Notation Control Structures. Appendix F. TLB and Cache Control. Appendix G. Memory Ordering Model. Appendix H. Address Formation Details. Appendix I. Programming Notes. Appendix J. PA-RISC 2 Instruction Completers & Pseudo-Ops.

SynopsisFor system designers and analysts, system software programmers, application developers, and technical managers. Hewlett-Packard's PA-RISC architecture is one of the most mature Reduced Instruction Set Computer designs in the industry. This book is the first publicly available, detailed description of the next revision of the PA-RISC architecture. Covers the RISC characteristics of PA-RISC, PA-RISC processing resources, addressing and access control, control flow, interruptions, and an overview of the instruction set and floating point corprocessor., Synthesizing the literature from related fields including macroeconomics, technology transfer, and innovation, the author's rigorous methodology shows that Total Factor Productivity is positively related to GDP and is mediated by research and development., Hewlett-Packard's PA-RISC architecture is one of the most mature Reduced Instruction Set Computer designs in the industry. This book is the first publicly available, detailed description of the next revision of the PA-RISC architecture. Covers the RISC characteristics of PA-RISC, PA- RISC processing resources, addressing and access control, control flow, interruptions, and an overview of the instruction set and floating point corprocessor. For system designers and analysts, system software programmers, application developers, and technical managers.

LC Classification NumberQA76.8.H48K36 1996