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RTL Modeling with SystemVerilog for Simulation and Synthesis : Using SystemVerilog for ASIC and FPGA Design by Stuart Sutherland (2017, Trade Paperback)

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Title: Rtl Modeling With Systemverilog For Simulation And Synthesis: Using Systemverilog For Asic And Fpga Design. Number of Pages: 488. Weight: 1.42 lbs. Publication Date: 2017-06-10. Publisher: Createspace Independent Publishing Platform.

About this product

Product Identifiers

PublisherCreateSpace

ISBN-101546776346

ISBN-139781546776345

eBay Product ID (ePID)247394815

Product Key Features

Book TitleRTL Modeling with SystemVerilog for Simulation and Synthesis : Using SystemVerilog for ASIC and FPGA Design

Number of Pages488 Pages

LanguageEnglish

TopicElectronics / Digital

Publication Year2017

GenreTechnology & Engineering

AuthorStuart Sutherland

FormatTrade Paperback

Dimensions

Item Height1.1 in

Item Weight28.9 Oz

Item Length9 in

Item Width6 in

Additional Product Features

Intended AudienceTrade

SynopsisThis book is both a tutorial and a reference for engineers who use the SystemVerilog Hardware Description Language (HDL) to design ASICs and FPGAs. The book shows how to write SystemVerilog models at the Register Transfer Level (RTL) that simulate and synthesize correctly, with a focus on proper coding styles and best practices. SystemVerilog is the latest generation of the original Verilog language, and adds many important capabilities to efficiently and more accurately model increasingly complex designs. This book reflects the SystemVerilog-2012/2017 standards. This book is for engineers who already know, or who are learning, digital design engineering. The book does not present digital design theory; it shows how to apply that theory to write RTL models that simulate and synthesize correctly. The creator of the original Verilog Language, Phil Moorby says about this book (an excerpt from the book's Foreword): "Many published textbooks on the design side of SystemVerilog assume that the reader is familiar with Verilog, and simply explain the new extensions. It is time to leave behind the stepping-stones and to teach a single consistent and concise language in a single book, and maybe not even refer to the old ways at all If you are a designer of digital systems, or a verification engineer searching for bugs in these designs, then SystemVerilog will provide you with significant benefits, and this book is a great place to learn the design aspects of SystemVerilog.", This book is both a tutorial and a reference for engineers who use the SystemVerilog Hardware Description Language (HDL) to design ASICs and FPGAs. The book shows how to write SystemVerilog models at the Register Transfer Level (RTL) that simulate and synthesize correctly, with a focus on proper coding styles and best practices.SystemVerilog is the latest generation of the original Verilog language, and adds many important capabilities to efficiently and more accurately model increasingly complex designs. This book reflects the SystemVerilog-2012/2017 standards. This book is for engineers who already know, or who are learning, digital design engineering. The book does not present digital design theory; it shows how to apply that theory to write RTL models that simulate and synthesize correctly. The creator of the original Verilog Language, Phil Moorby says about this book (an excerpt from the book's Foreword): "Many published textbooks on the design side of SystemVerilog assume that the reader is familiar with Verilog, and simply explain the new extensions. It is time to leave behind the stepping-stones and to teach a single consistent and concise language in a single book, and maybe not even refer to the old ways at all! If you are a designer of digital systems, or a verification engineer searching for bugs in these designs, then SystemVerilog will provide you with significant benefits, and this book is a great place to learn the design aspects of SystemVerilog."