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Advanced Asic Chip Synthesis : Using Synopsys® Design Compiler® Physical Compiler® and Primetime® by Himanshu Bhatnagar (2001, Hardcover)
AlibrisBooks (464164)
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- Buy It NowAdvanced ASIC Chip Synthesis: Using Synopsys(r) Design Compiler(tm) Physical
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About this product
Product Identifiers
PublisherSpringer
ISBN-100792376447
ISBN-139780792376446
eBay Product ID (ePID)2173514
Product Key Features
Number of PagesXxvi, 328 Pages
Publication NameAdvanced ASIC Chip Synthesis : Using Synopsys® Design Compiler® Physical Compiler® and Primetime®
LanguageEnglish
SubjectCad-Cam, Electronics / Circuits / General, Electrical, Compilers
Publication Year2001
FeaturesRevised
TypeTextbook
AuthorHimanshu Bhatnagar
Subject AreaComputers, Technology & Engineering
FormatHardcover
Dimensions
Item Weight53.6 Oz
Item Length9.2 in
Item Width6.1 in
Additional Product Features
Edition Number2
Intended AudienceScholarly & Professional
LCCN2001-050707
Number of Volumes1 vol.
IllustratedYes
Edition DescriptionRevised edition
Table Of ContentAsic Design Methodology.- Tutorial.- Basic Concepts.- Synopsys Technology Library.- Partitioning and Coding Styles.- Constraining Designs.- Optimizing Designs.- Design for Test.- Links to Layout and Post Layout Optimization.- Physical Synthesis.- SDF Generation.- PrimeTime Basics.- Static Timing Analysis.
SynopsisAdvanced ASIC Chip Synthesis: Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime®, Second Edition describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail. The emphasis of this book is on real-time application of Synopsys tools, used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, sub-micron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, physical synthesis, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-around described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basis of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solution. Target audiences for this book are practicing ASIC design engineers and masters level students undertaking advanced VLSI courses on ASIC chip design and DFT techniques., Advanced ASIC Chip Synthesis: Using Synopsys(R) Design Compiler(R) Physical Compiler(R) and PrimeTime(R), Second Edition describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail. The emphasis of this book is on real-time application of Synopsys tools, used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, sub-micron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, physical synthesis, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-around described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basis of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solution. Target audiences for this book are practicing ASIC design engineers and masters level students undertaking advanced VLSI courses on ASIC chip design and DFT techniques.
LC Classification NumberTK7867-7867.5
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