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Introduction to SystemVerilog - Paperback, by Mehta Ashok B. - New
US $68.03
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eBay item number:126460767898
Item specifics
- Condition
- Type
- Textbook
- ISBN
- 9783030713218
- Publication Year
- 2022
- Format
- Trade Paperback
- Language
- English
- Book Title
- Introduction to Systemverilog
- Item Length
- 9.3in
- Publisher
- Springer International Publishing A&G
- Genre
- Technology & Engineering, Computers
- Topic
- Systems Architecture / General, Engineering (General), Electronics / Circuits / General
- Item Width
- 6.1in
- Item Weight
- 55 Oz
- Number of Pages
- Xxxv, 852 Pages
About this product
Product Information
This book provides a hands-on, application-oriented guide to the entire IEEE standard 1800 SystemVerilog language. Readers will benefit from the step-by-step approach to learning the language and methodology nuances, which will enable them to design and verify complex ASIC/SoC and CPU chips. The author covers the entire spectrum of the language, including random constraints, SystemVerilog Assertions, Functional Coverage, Class, checkers, interfaces, and Data Types, among other features of the language. Written by an experienced, professional end-user of ASIC/SoC/CPU and FPGA designs, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the complex task of multi-million gate ASIC designs. Provides comprehensive coverage of the entire IEEE standard SystemVerilog language; Covers important topics such as constrained random verification, SystemVerilog Class, Assertions, Functional coverage, data types, checkers, interfaces, processes and procedures, among other language features; Uses easy to understand examples and simulation logs; examples are simulatable and will be provided online; Written by an experienced, professional end-user of ASIC/SoC/CPU and FPGA designs. This is quite a comprehensive work. It must have taken a long time to write it. I really like that the author has taken apart each of the SystemVerilog constructs and talks about them in great detail, including example code and simulation logs. For example, there is a chapter dedicated to arrays, and another dedicated to queues - that is great to have! The Language Reference Manual (LRM) is quite dense and difficult to use as a text for learning the language. This book explains semantics at a level of detail that is not possible in an LRM. This is the strength of the book. This will be an excellent book for novice users and as a handy reference for experienced programmers. Mark Glasser Cerebras Systems
Product Identifiers
Publisher
Springer International Publishing A&G
ISBN-10
3030713210
ISBN-13
9783030713218
eBay Product ID (ePID)
19057290278
Product Key Features
Book Title
Introduction to Systemverilog
Format
Trade Paperback
Language
English
Topic
Systems Architecture / General, Engineering (General), Electronics / Circuits / General
Publication Year
2022
Genre
Technology & Engineering, Computers
Number of Pages
Xxxv, 852 Pages
Dimensions
Item Length
9.3in
Item Width
6.1in
Item Weight
55 Oz
Additional Product Features
Number of Volumes
1 Vol.
Lc Classification Number
Tk7867-7867.5
Table of Content
Introduction.- Data Types.- Arrays.- Queues.- Structures.- Packages.- Class.- SystemVerilog 'module'.- SystemVerilog 'program'.- Interfaces.- Operators.- Constrained Random Test Generation and Verification.- SystemVerilog Assertions.- Functional Coverage.- SystemVerilog Processes.- Procedural programming statements.- Processes.- Tasks and Functions.- Clocking Blocks.- Checkers.- Inter-process communication and synchronization.- Utility System tasks and functions.
Copyright Date
2021
Dewey Decimal
621.392
Dewey Edition
23
Illustrated
Yes
Item description from the seller
Seller assumes all responsibility for this listing.
eBay item number:126460767898
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