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Writing Testbenches: Functional - Hardcover, by Bergeron Janick - Very Good
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eBay item number:126014333087
Item specifics
- Condition
- Book Title
- Writing Testbenches: Functional Verification of HDL Models
- ISBN
- 9781402074011
- Subject Area
- Computers, Technology & Engineering
- Publication Name
- Writing Testbenches : Functional Verification of Hdl Models
- Publisher
- Springer
- Item Length
- 9.3 in
- Subject
- Computer Science, Electronics / Circuits / Integrated, Electronics / Circuits / General, Compilers, Software Development & Engineering / Systems Analysis & Design
- Publication Year
- 2003
- Type
- Textbook
- Format
- Hardcover
- Language
- English
- Features
- Revised
- Item Weight
- 69.1 Oz
- Item Width
- 6.1 in
- Number of Pages
- Xxx, 478 Pages
About this product
Product Information
mental improvements during the same period. What is clearly needed in verification techniques and technology is the equivalent of a synthesis productivity breakthrough. In the second edition of Writing Testbenches, Bergeron raises the verification level of abstraction by introducing coverage-driven constrained-random transaction-level self-checking testbenches- all made possible through the introduction of hardware verification languages (HVLs), such as e from Verisity and OpenVera from Synopsys. The state-of-art methodologies described in Writing Test- benches will contribute greatly to the much-needed equivalent of a synthesis breakthrough in verification productivity. I not only highly recommend this book, but also I think it should be required reading by anyone involved in design and verification of today's ASIC, SoCs and systems. Harry Foster Chief Architect Verplex Systems, Inc. xviii Writing Testbenches: Functional Verification of HDL Models PREFACE If you survey hardware design groups, you will learn that between 60% and 80% of their effort is now dedicated to verification.
Product Identifiers
Publisher
Springer
ISBN-10
1402074018
ISBN-13
9781402074011
eBay Product ID (ePID)
2344666
Product Key Features
Number of Pages
Xxx, 478 Pages
Language
English
Publication Name
Writing Testbenches : Functional Verification of Hdl Models
Publication Year
2003
Subject
Computer Science, Electronics / Circuits / Integrated, Electronics / Circuits / General, Compilers, Software Development & Engineering / Systems Analysis & Design
Features
Revised
Type
Textbook
Subject Area
Computers, Technology & Engineering
Format
Hardcover
Dimensions
Item Weight
69.1 Oz
Item Length
9.3 in
Item Width
6.1 in
Additional Product Features
Edition Number
2
Intended Audience
Scholarly & Professional
LCCN
2003-041995
Reviews
"Brilliant. Janick Bergeron has built on his ground-breaking first version of Writing Testbenches in this second edition..." (Grant Martin, Fellow, Cadence Berkeley Labs) "In the latest edition, Mr. Bergeron continues to keep pace with the industry while providing world-class solutions to the verification problem..." (Chris Macinonski, Senior Engineer, Qualis Design Corp.) "Many companies out there now owe their current verification methodologies to this book. From it they have learned the secrets of efficiency, effectiveness and re-use as they apply to verification..." (Brian Bailey, Chief Technologist, Mentor Graphics Corp.) "A must have bible for understanding verification issues and techniques with HDLs and HVLs, and for writing effective, readable and reusable testbenches within a best-in-class verification process." (Ben Cohen, VhdlCohen Training), "Brilliant. Janick Bergeron has built on his ground-breaking first version of Writing Testbenches in this second edition..." (Grant Martin, Fellow, Cadence Berkeley Labs) "In the latest edition, Mr. Bergeron continues to keep pace with the industry while providing world-class solutions to the verification problem..."(Chris Macinonski, Senior Engineer, Qualis Design Corp.) "Many companies out there now owe their current verification methodologies to this book. From it they have learned the secrets of efficiency, effectiveness and re-use as they apply to verification..." (Brian Bailey, Chief Technologist, Mentor Graphics Corp.) "A must have bible for understanding verification issues and techniques with HDLs and HVLs, and for writing effective, readable and reusable testbenches within a best-in-class verification process." (Ben Cohen, VhdlCohen Training)
Number of Volumes
1 Vol.
Illustrated
Yes
Edition Description
Revised Edition
Lc Classification Number
Tk7867-7867.5
Table of Content
1 What is Verification?.- What is a Testbench?.- The Importance of Verification.- Reconvergence Model.- The Human Factor.- What Is Being Verified?.- Functional Verification Approaches.- Testing Versus Verification.- Design and Verification Reuse.- The Cost of Verification.- Summary.- 2 Verification Tools.- Linting Tools.- Simulators.- Verification Intellectual Property.- Waveform Viewers.- Functional Coverage.- Verification Languages.- Assertions.- Revision Control.- Issue Tracking.- Metrics.- Summary.- 3 The Verification Plan.- The Role of the Verification Plan.- Levels of Verification.- Verification Strategies.- From Specification to Features.- Directed Testbenches Approach.- Coverage-Driven Random-Based Approach.- Summary.- 4 High-Level Modeling.- Behavioral versus RTL Thinking.- You Gotta Have Style!.- Structure of Behavioral Code.- Data Abstraction.- Object-Oriented Programming.- Aspect-Oriented Programming.- The Parallel Simulation Engine.- Race Conditions.- Verilog Portability Issues.- Summary.- 5 Stimulus and Response.- Reference Signals.- Simple Stimulus.- Simple Output.- Complex Stimulus.- Bus-Functional Models.- Response Monitors.- Transaction-Level Interface.- Summary.- 6 Architecting Testbenches.- Test Harness.- VHDL Test Harness.- Design Configuration.- Self-Checking Testbenches.- Directed Stimulus.- Random Stimulus.- Summary.- 7 Simulation Management.- Behavioral Models.- Pass or Fail?.- Managing Simulations.- Regression.- Summary.- Appendix A Coding Guidelines.- Directory Structure.- VHDL Specific.- Verilog Specific.- General Coding Guidelines.- Comments.- Layout.- Syntax.- Debugging.- Naming Guidelines.- Capitalization.- Identifiers.- Constants.- HDL & HVL Specific.- Filenames.- HDL Coding Guidelines.- Structure.- Layout.- VHDL Specific.- Verilog Specific.- Appendix B Glossary.- Afterwords.
Copyright Date
2003
Item description from the seller
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