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High Speed CMOS Design Styles by Kerry Bernstein: New
US $188.13
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Item specifics
- Condition
- Book Title
- High Speed CMOS Design Styles
- Publication Date
- 1998-08-31
- Pages
- 353
- ISBN
- 9780792382201
- Subject Area
- Computers, Technology & Engineering
- Publication Name
- High Speed Cmos Design Styles
- Publisher
- Springer
- Item Length
- 9.3 in
- Subject
- Electronics / Semiconductors, Electronics / Circuits / Vlsi & Ulsi, Cad-Cam, Electronics / Circuits / General, Electrical
- Publication Year
- 1998
- Type
- Textbook
- Format
- Hardcover
- Language
- English
- Item Weight
- 55 Oz
- Item Width
- 6.1 in
- Number of Pages
- Xix, 353 Pages
About this product
Product Identifiers
Publisher
Springer
ISBN-10
079238220X
ISBN-13
9780792382201
eBay Product ID (ePID)
7038693187
Product Key Features
Number of Pages
Xix, 353 Pages
Publication Name
High Speed Cmos Design Styles
Language
English
Publication Year
1998
Subject
Electronics / Semiconductors, Electronics / Circuits / Vlsi & Ulsi, Cad-Cam, Electronics / Circuits / General, Electrical
Type
Textbook
Subject Area
Computers, Technology & Engineering
Format
Hardcover
Dimensions
Item Weight
55 Oz
Item Length
9.3 in
Item Width
6.1 in
Additional Product Features
Intended Audience
Scholarly & Professional
LCCN
98-028409
Dewey Edition
21
Number of Volumes
1 vol.
Illustrated
Yes
Dewey Decimal
621.3815/2
Table Of Content
1 Process Variability.- 1.1 Introduction.- 1.2 Front-End-Of-Line Variability Considerations.- 1.3 Charge Loss Mechanisms.- 1.4 Back-End-Of-Line Variability Considerations.- 1.5 Summary.- 2 Non-Clocked Logic Styles.- 2.1 Introduction.- 2.2 Static CMOS Structures.- 2.3 DCVS Logic.- 2.4 Non-Clocked Pass-Gate Families.- 2.5 Summary.- 3 Clocked Logic Styles.- 3.1 Introduction.- 3.2 Single-Rail Domino Logic Styles.- 3.3 Alternating-Polarity Domino Approaches.- 3.4 Dual-Rail Domino Structures.- 3.5 Latched Domino Structures.- 3.6 Clocked Pass-Gate Logic.- 3.7 Summary.- 4 Circuit Design Margin and Design Variability.- 4.1 Introduction.- 4.2 Process Induced Variation.- 4.3 Design Induced Variation.- 4.4 Application Induced Variation.- 4.5 Noise.- 4.6 Design Margin Budgeting.- 4.7 Summary.- 5 Latching Strategies.- 5.1 Introduction.- 5.2 Basic Latch Design.- 5.3 Latching Single-Ended Logic.- 5.4 Latching Differential Logic.- 5.5 Race Free Latches for Precharged Logic.- 5.6 Asynchronous Latch Techniques.- 5.7 Summary.- 6 Interface Techniques.- 6.1 Introduction.- 6.2 Signaling Standards.- 6.3 Chip-to-chip Communication Networks.- 6.4 ESD Protection.- 6.5 Driver Design Techniques.- 6.6 Receiver Design Techniques.- 6.7 Summary.- 7 Clocking Styles.- 7.1 Introduction.- 7.2 Clock Jitter and Skew.- 7.3 Clock Generation.- 7.4 Clock Distribution.- 7.5 Single Phase Clocking.- 7.6 Multi-Phase Clocking.- 7.7 Asynchronous Techniques.- 7.8 Summary.- 8 Slack Borrowing and Time Stealing.- 8.1 Introduction.- 8.2 Slack Borrowing.- 8.3 Time Stealing.- 8.4 Summary.- 9 Future Technology.- 9.1 Introduction.- 9.2 Classical Scaling Theory.- 9.3 Industry Trends Define Scaling Law.- 9.4 Challenges Presented by I/S Scaling.- 9.5 Possible Directions.
Synopsis
High Speed CMOS Design Styles is written for the graduate-level student or practicing engineer who is primarily interested in circuit design. It is intended to provide practical reference, or horse-sense', to mechanisms typically described with a more academic slant. This book is organized so that it can be used as a textbook or as a reference book. High Speed CMOS Design Styles provides a survey of design styles in use in industry, specifically in the high speed microprocessor design community. Logic circuit structures, I/O and interface, clocking, and timing schemes are reviewed and described. Characteristics, sensitivities and idiosyncrasies of each are highlighted. High Speed CMOS Design Styles also pulls together and explains contributors to performance variability that are associated with process, applications conditions and design. Rules of thumb and practical references are offered. Each of the general circuit families is then analyzed for its sensitivity and response to this variability. High Speed CMOS Design Styles is an excellent source of ideas and a compilation of observations that highlight how different approaches trade off critical parameters in design and process space., High Speed CMOS Design Styles is written for the graduate-level student or practicing engineer who is primarily interested in circuit design. It is intended to provide practical reference, or 'horse-sense', to mechanisms typically described with a more academic slant. This book is organized so that it can be used as a textbook or as a reference book. High Speed CMOS Design Styles provides a survey of design styles in use in industry, specifically in the high speed microprocessor design community. Logic circuit structures, I/O and interface, clocking, and timing schemes are reviewed and described. Characteristics, sensitivities and idiosyncrasies of each are highlighted. High Speed CMOS Design Styles also pulls together and explains contributors to performance variability that are associated with process, applications conditions and design. Rules of thumb and practical references are offered. Each of the general circuit families is then analyzed for its sensitivity and response to this variability. High Speed CMOS Design Styles is an excellent source of ideas and a compilation of observations that highlight how different approaches trade off critical parameters in design and process space.
LC Classification Number
TK7867-7867.5
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